FIG. 1 is a schematic circuit diagram illustrating a conventional charge pump regulator. As shown in FIG. 1, the charge pump regulator 100 comprises a charge pump circuit 110, a feedback detector 120 and a clock generator 130. An output signal Vout is generated by the charge pump regulator 100 and transmitted to a bulk capacitor Cb.
The charge pump circuit 110 receives a source clock CK and generates the output signal Vout. When the source clock CK is maintained at a fixed level, the magnitude of the output signal Vout gradually decreases. Whereas, when the source clock CK is switched between a high level state and a low level state, the magnitude of the output signal Vout gradually increases according to a signal edge (e.g. a rising edge or a falling edge) of the source clock CK.
Moreover, the feedback detector 120 comprises a voltage divider 122 and a comparator 124. The voltage divider 122 consists of two resistors R1 and R2. The voltage divider 122 receives the output signal Vout and generates a feedback signal Vfb. A negative input terminal of the comparator 124 receives the feedback signal Vfb. A positive input terminal of the comparator 124 receives a reference voltage Vref. An output terminal of the comparator 124 generates an enabling signal EN. In the voltage divider 122, the relationship between the output signal Vout and the feedback signal Vfb is expressed as: Vfb=(R2×Vout)/(R1+R2). As the magnitude of the output signal Vout increases, the magnitude of the feedback signal Vfb increases. On the other hand, as the magnitude of the output signal Vout decreases, the magnitude of the feedback signal Vfb decreases.
Moreover, after the clock generator 130 receives the enabling signal EN, the clock generator 130 generates the source clock CK according to the enabling signal EN. Moreover, if the magnitude of the feedback signal Vfb is higher than the magnitude of the reference voltage Vref, the enabling signal EN is in the low level state to disable the clock generator 130 and the source clock CK is maintained at the fixed level. Consequently, the magnitude of the output signal Vout gradually decreases. If the magnitude of the feedback signal Vfb is lower than the magnitude of the reference voltage Vref, the enabling signal EN is in the high level state to enable the clock generator 130. Consequently, the source clock CK is switched between the high level state and the low level state, and the magnitude of the output signal Vout gradually increases according to the signal edge of the source clock CK.
When the charge pump regulator 100 reaches the steady state, the output signal Vout is maintained at a level near a target voltage. The target voltage is equal to Vref×(1+R1/R2). However, the output signal Vout contains ripple.